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19-5106; Rev 2; 1/11
KIT ATION EVALU LE B AVAILA
4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs
General Description Features
o o o o o o o o o o o o o o o 16-Bit ADC (MAX11047/MAX11048/MAX11049) 14-Bit ADC (MAX11057/MAX11058/MAX11059) 8-Channel ADC (MAX11047/MAX11057) 6-Channel ADC (MAX11048/MAX11058) 4-Channel ADC (MAX11049/MAX11059) Single Analog and Digital Supply High-Impedance Inputs Up to 1G On-Chip T/H Circuit for Each Channel Fast 3s Conversion Time High Throughput: 250ksps for Each Channel 16-/14-Bit, High-Speed, Parallel Interface Internal Clocked Conversions 10ns Aperture Delay 100ps Channel-to-Channel T/H Matching Low Drift, Accurate 4.096V Internal Reference Providing an Input Range of 0 to 5V o External Reference Range of 3.0V to 4.25V, Allowing Full-Scale Input Ranges of +3.7V to +5.2V o 56-Pin TQFN (8mm x 8mm) and 64-Pin TQFP (10mm x 10mm) Packages o Evaluation Kit Available (MAX11046EVKIT+)
MAX11047-MAX11049/MAX11057-MAX11059
The MAX11047/MAX11048/MAX11049 and MAX11057/ MAX11058/MAX11059 16-bit/14-bit ADCs offer 4, 6, or 8 independent input channels. Featuring independent track and hold (T/H) and SAR circuitry, these parts provide simultaneous sampling at 250ksps for each channel. The devices accept a 0 to +5V input. All inputs are overrange protected with internal 20mA input clamps providing overrange protection with a simple external resistor. Other features include a 4MHz T/H input bandwidth, internal clock, and internal or external reference. A 20MHz, bidirectional, parallel interface provides the conversion results and accepts digital configuration inputs. The devices operate with a 4.75V to 5.25V analog supply and a separate flexible 2.7V to 5.25V digital supply for interfacing with the host without a level shifter. The MAX11047/MAX11048/MAX11049 are available in a 56-pin TQFN and 64-pin TQFP packages while the MAX11057/ MAX11058/MAX11059 are available in TQFP only. All devices operate over the extended -40C to +85C temperature range.
Applications
Automatic Test Equipment Power-Factor Monitoring and Correction Power-Grid Protection Multiphase Motor Control Vibration and Waveform Analysis
Functional Diagram
AVDD DVDD DB15**
Ordering Information
PART MAX11047ETN+ MAX11047ECB+ MAX11048ETN+ MAX11048ECB+ MAX11049ETN+ MAX11049ECB+ MAX11057ECB+ MAX11058ECB+ MAX11059ECB+ PIN-PACKAGE 56 TQFN-EP* 64 TQFP-EP* 56 TQFN-EP* 64 TQFP-EP* 56 TQFN-EP* 64 TQFP-EP* 64 TQFP-EP* 64 TQFP-EP* 64 TQFP-EP* CHANNELS 4 4 6 6 8 8 4 6 8
REFIO BANDGAP REFERENCE 10k AGND MAX11047/MAX11048/MAX11049/ MAX11057/MAX11058/MAX11059 INT REF REF BUF EXT REF AGNDS CH7 CLAMP S/H 16-/14-BIT ADCs
BIDIRECTIONAL DRIVERS
CLAMP
S/H
16-/14-BIT ADCs
8 x 16-/14-BIT REGISTERS
CH0
DB4 DB3/CR3 DB0/CR0
CONFIGURATION REGISTERS INTERFACE AND CONTROL
WRb RDb CSb CONVST SHDN EOCb DGND RDC RDC_SENSE*
Note: All devices are specified over the -40C to +85C operating temperature range. +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad.
*CONNECTED INTERNALLY ON THE TQFN PARTS **MAX11047/MAX11048/MAX11049 MAX11049/MAX11059
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs MAX11047-MAX11049/MAX11057-MAX11059
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND ........................................................-0.3V to +6V DVDD to AGND and DGND .....................................-0.3V to +6V DGND to AGND.....................................................-0.3V to +0.3V AGNDS to AGND...................................................-0.3V to +0.3V CH0-CH7 to AGND ...............................................-2.5V to +7.5V REFIO, RDC to AGND ..................................-0.3V to the lower of (AVDD + 0.3V) and +6V EOC, WR, RD, CS, CONVST to AGND.........-0.3V to the lower of (DVDD + 0.3V) and +6V DB0-DB15 to AGND ....................................-0.3V to the lower of (DVDD + 0.3V) and +6V Maximum Current into Any Pin Except AVDD, DVDD, AGND, DGND ...........................................................................50mA Continuous Power Dissipation (TA = +70C) 56-Pin TQFN (derated 47.6mW/C above +70C) ..3809.5mW 64-Pin TQFP (derate 43.5mW/C above +70C .........3478mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C Soldering Temperature (reflow) .......................................+260C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VAVDD = 4.75V to 5.25V, VDVDD = +2.7V to 5.25V, VAGNDS = VAGND = VDGND = 0V, VREFIO = internal reference, CRDC = 4 x 33F, CREFIO = 0.1F, CAVDD = 4 x 0.1F || 10F, CDVDD = 3 x 0.1F || 10F; all digital inputs at DVDD or DGND, unless otherwise noted. TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER STATIC PERFORMANCE (Note 1) Resolution Integral Nonlinearity N INL MAX11047/MAX11048/MAX11049 MAX11057/MAX11058/MAX11059 MAX11047/MAX11048/MAX11049 MAX11057/MAX11058/MAX11059 Differential Nonlinearity DNL MAX11047/MAX11048/MAX11049 MAX11057/MAX11058/MAX11059 No Missing Codes Offset Error Offset Temperature Coefficient Channel Offset Matching Gain Error Positive Full-Scale Error Positive Full-Scale Error Matching Channel Gain-Error Matching Gain Temperature Coefficient DYNAMIC PERFORMANCE MAX11047/MAX11048/MAX11049, f IN = 10kHz, full-scale input MAX11057/MAX11058/MAX11059, f IN = 10kHz, full-scale input 90.7 84.5 92.3 dB 85.3 Between all channels 0.6 MAX11047/MAX11048/MAX11049 MAX11057/MAX11058/MAX11059 16 14 -2 -0.9 > -1 -0.6 16 14 0.001 0.8 0.01 0.012 0.017 0.01 0.01 0.012 0.65 0.2 0.7 0.2 +2 +0.9 < +1.2 +0.7 Bits %FSR V/C %FSR %FSR %FSR %FSR %FSR ppm/C LSB Bits LSB SYMBOL CONDITIONS MIN TYP MAX UNITS
Signal-to-Noise Ratio
SNR
2
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4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs
ELECTRICAL CHARACTERISTICS (continued)
VAVDD = 4.75V to 5.25V, VDVDD = +2.7V to 5.25V, VAGNDS = VAGND = VDGND = 0V, VREFIO = internal reference, CRDC = 4 x 33F, CREFIO = 0.1F, CAVDD = 4 x 0.1F || 10F, CDVDD = 3 x 0.1F || 10F; all digital inputs at DVDD or DGND, unless otherwise noted. TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Signal-to-Noise and Distortion Ratio SYMBOL CONDITIONS MAX11047/MAX11048/MAX11049, f IN = 10kHz, full-scale input MAX11057/MAX11058/MAX11059, f IN = 10kHz, full-scale input MAX11047/MAX11048/ f IN = 10kHz, MAX11049 full-scale input MAX11057/MAX11058/ MAX11059 MAX11047/MAX11048/ f IN = 10kHz, MAX11049 full-scale input MAX11057/MAX11058/ MAX11059 f IN = 60Hz, full scale and ground on adjacent channel (Note 2) MIN 90.5 84.5 98 95 TYP 92 dB 85.2 108 dB 108 -108 -108 -126 -98 dB -95 -100 dB MAX UNITS
MAX11047-MAX11049/MAX11057-MAX11059
SINAD
Spurious-Free Dynamic Range
SFDR
Total Harmonic Distortion
THD
Channel-to-Channel Crosstalk ANALOG INPUTS (CH0-CH7) Input Voltage Range Input Leakage Current Input Capacitance Input-Clamp Protection Current TRACK AND HOLD Throughput Rate Acquisition Time Full-Power Bandwidth Aperture Delay Aperture-Delay Matching Aperture Jitter INTERNAL REFERENCE REFIO Voltage REFIO Temperature Coefficient EXTERNAL REFERENCE Input Current REF Voltage Input Range REF Input Capacitance VREF VREF tACQ
(Note 3)
0 -1 15
1.22 x VREFIO +1 +20 250
V A pF mA ksps s
Each input simultaneously Per channel
-20
1 -3dB point -0.1dB point 4 > 0.2 10 100 50 4.080 4.096 4 -10 3.00 15 +10 4.25 4.112
MHz ns ps psRMS V ppm/C A V pF V 0.8 V pF 10 A
DIGITAL INPUTS (CR0-CR3, RD, WR, CS, CONVST) Input-Voltage High Input-Voltage Low Input Capacitance Input Current VIH VIL CIN I IN VIN = 0 or VDVDD VDVDD = 2.7V to 5.25V VDVDD = 2.7V to 5.25V 10 2
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4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs MAX11047-MAX11049/MAX11057-MAX11059
ELECTRICAL CHARACTERISTICS (continued)
VAVDD = 4.75V to 5.25V, VDVDD = +2.7V to 5.25V, VAGNDS = VAGND = VDGND = 0V, VREFIO = internal reference, CRDC = 4 x 33F, CREFIO = 0.1F, CAVDD = 4 x 0.1F || 10F, CDVDD = 3 x 0.1F || 10F; all digital inputs at DVDD or DGND, unless otherwise noted. TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER SYMBOL CONDITIONS MIN VDVDD 0.4 0.4 VIH or VCS VIH or VCS VIH VIH 4.75 2.70 VDVDD = 3.3V (Note 4) For DVDD For AVDD PSR VAVDD = 4.9V to 5.1V (Note 5) MAX11047 MAX11057 4.75 2.70 VDVDD = 3.3V (Note 4) For DVDD For AVDD PSR VAVDD = 4.9V to 5.1V (Note 5) MAX11048 MAX11058 4.75 2.70 VDVDD = 3.3V (Note 4) For DVDD For AVDD PSR VAVDD = 4.9V to 5.1V (Note 5) MAX11049 MAX11059 1.2 0.3 3 1 Sample quiet time (Note 6) 500 1.2 0.3 5.25 5.25 39 7 10 10 1.2 0.3 5.25 5.25 32 6.5 10 10 15 5.25 5.25 25 5.5 10 10 10 TYP MAX UNITS DIGITAL OUTPUTS (DB0-DB15, EOC) Output-Voltage High Output-Voltage Low Three-State Leakage Current Three-State Output Capacitance POWER SUPPLIES (MAX11047/MAX11057) Analog Supply Voltage Digital Supply Voltage Analog Supply Current Digital Supply Current Shutdown Current Shutdown Current Power-Supply Rejection AVDD DVDD IAVDD IDVDD V V mA mA A A LSB VOH VOL I SOURCE = 1.2mA I SINK = 1mA DB0-DB15, VRD DB0-DB15, VRD V V A pF
POWER SUPPLIES (MAX11048/MAX11058) Analog Supply Voltage Digital Supply Voltage Analog Supply Current Digital Supply Current Shutdown Current Shutdown Current Power-Supply Rejection AVDD DVDD IAVDD IDVDD V V mA mA A A LSB
POWER SUPPLIES (MAX11049/MAX11059) Analog Supply Voltage Digital Supply Voltage Analog Supply Current Digital Supply Current Shutdown Current Shutdown Current Power-Supply Rejection TIMING CHARACTERISTICS (Note 4) CONVST Rise to EOC Fall Acquisition Time CS Rise to CONVST Rise tCON tACQ tQ Conversion time (Note 6) s s ns AVDD DVDD IAVDD IDVDD V V mA mA A A LSB
4
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4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs
ELECTRICAL CHARACTERISTICS (continued)
VAVDD = 4.75V to 5.25V, VDVDD = +2.7V to 5.25V, VAGNDS = VAGND = VDGND = 0V, VREFIO = internal reference, CRDC = 4 x 33F, CREFIO = 0.1F, CAVDD = 4 x 0.1F || 10F, CDVDD = 3 x 0.1F || 10F; all digital inputs at DVDD or DGND, unless otherwise noted. TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER CONVST Rise to EOC Rise EOC Fall to CONVST Fall CONVST Low Time CS Fall to WR Fall WR Low Time CS Rise to WR Rise Input Data Setup Time Input Data Hold Time CS Fall to RD Fall RD Low Time RD Rise to CS Rise RD High Time RD Fall to Data Valid RD Rise to Data Hold Time SYMBOL t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 (Note 7) 5 CONVST mode B0 = 0 only (Note 7) CONVST mode B0 = 1 only 0 20 0 20 0 10 0 0 30 0 10 35 CONDITIONS MIN TYP 65 MAX 140 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MAX11047-MAX11049/MAX11057-MAX11059
Note 1: Note 2: Note 3: Note 4:
See the Definitions section at the end of the data sheet. Tested with alternating channels modulated at full scale and ground. See the Input Range and Protection section. CLOAD= 30pF on DB0-DB15 and EOC. Inputs (CH0-CH7) alternate between full scale and zero scale. fCONV = 250ksps. All data is read out. Note 5: Defined as the change in positive full scale caused by a 2% variation in the nominal supply voltage. Note 6: It is recommended that RD, WR, and CS are kept high for the quiet time (tQ) and conversion time (tCON). Note 7: Guaranteed by design.
Typical Operating Characteristics
(VAVDD = 5V, VDVDD = 3.3V, TA = +25C, fSAMPLE = 250ksps, internal reference, unless otherwise noted.)
INTEGRAL NONLINEARITY (INL) vs. CODE FOR MAX1104_
MAX11047 toc01
DIFFERENTIAL NONLINEARITY (DNL) vs. CODE FOR MAX1104_
0.8 0.6 0.4 DNL (LSBs) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 VAVDD = 5.0V VDVDD = 3.3V fSAMPLE = 250ksps TA = +25C VRDC = 4.096V 16384 32768 49152 65536 8192 24576 40960 57344 OUTPUT CODE (DECIMAL)
MAX11047 toc02
1.0 0.8 0.6 0.4 INL (LSBs) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 8192 16384 VAVDD = 5.0V VDVDD = 3.3V fSAMPLE = 250ksps TA = +25C VRDC = 4.096V
1.0
65536 32768 49152 24576 40960 57344 OUTPUT CODE (DECIMAL)
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4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs MAX11047-MAX11049/MAX11057-MAX11059
Typical Operating Characteristics (continued)
(VAVDD = 5V, VDVDD = 3.3V, TA = +25C, fSAMPLE = 250ksps, internal reference, unless otherwise noted.)
INL AND DNL vs. ANALOG SUPPLY VOLTAGE FOR MAX1104_
MAX11047 toc03
INL AND DNL vs. TEMPERATURE FOR MAX1104_
MAX INL 1.0 INL AND DNL (LSBs) 0.5 MAX DNL 0 -0.5 -1.0 -1.5 MIN DNL VAVDD = 5.0V VDVDD = 3.3V fSAMPLE = 250ksps VRDC = 4.096V 35 60 85 MIN INL IAVDD (mA)
MAX11047 toc04
ANALOG SUPPLY CURRENT vs. SUPPLY VOLTAGE
34 32 MAX11049 STATIC 30 28 26 MAX11048 STATIC 24 22 20 MAX11047 STATIC 18 4.75 4.85 4.95 5.05 5.15 5.25 VAVDD (V) MAX11047 CONVERTING TA = +25C fSAMPLE = 250ksps MAX11048 CONVERTING
MAX11047 toc05
1.5 MAX DNL 1.0 INL AND DNL (LSBs) 0.5 0 -0.5 -1.0 -1.5 4.75 4.85 4.95 MIN DNL VDVDD = 3.3V fSAMPLE = 250ksps TA = +25C VRDC = 4.096V 5.05 5.15 MAX INL MIN INL
1.5
36 MAX11049 CONVERTING
5.25
-40
-15
10
VAVDD (V)
TEMPERATURE (C)
ANALOG SUPPLY CURRENT vs. TEMPERATURE
MAX11047 toc06
DIGITAL SUPPLY CURRENT vs. SUPPLY VOLTAGE
TA = +25C fSAMPLE = 250ksps CDBxx = 15pF MAX11049 CONVERTING 8 IDVDD (mA) IDVDD (mA) 6 4 2 MAX11048 CONVERTING MAX11049/MAX11048/ MAX11047 STATIC MAX11047 CONVERTING 2.75 3.25 3.75 4.25 4.75 5.25 4.8 3.6 2.4 1.2 0 -40
MAX11047 toc07
DIGITAL SUPPLY CURRENT vs. TEMPERATURE
MAX11049 CONVERTING
MAX11047 toc08
12 10
7.2 6.0
34
MAX11049 CONVERTING MAX11049 STATIC
30 IAVDD (mA)
MAX11048 CONVERTING
MAX11048 CONVERTING MAX11047 CONVERTING VDVDD = 3.3V fSAMPLE = 250ksps CDBxx = 15pF -15 10 MAX11049/MAX11048/ MAX11047 STATIC
26 MAX11048 STATIC MAX11047 CONVERTING 22 MAX11047 STATIC 18 -40 -15 10 35 60 85 TEMPERATURE (C) VAVDD = 5.0V fSAMPLE = 250ksps
0 VDVDD (V)
35
60
85
TEMPERATURE (C)
ANALOG AND DIGITAL SHUTDOWN CURRENT vs. TEMPERATURE
MAX11047 toc09
ANALOG AND DIGITAL SHUTDOWN CURRENT vs. SUPPY VOLTAGE
MAX11047 toc09a
INTERNAL REFERENCE VOLTAGES vs. SUPPLY VOLTAGE
TA = +25C 4.09625 4.09620 VREF (V) 4.09615 4.09610 4.09605 VRDC
MAX11047 toc10
5
VAVDD = 5.0V VDVDD = 3.3V
5
TA = +25C
4.09630
SHUTDOWN CURRENT (A)
SHUTDOWN CURRENT (A)
4 IAVDD
4 IAVDD
3
3
2 IDVDD 1
2 IDVDD 1
4.09600 4.09595 VREFIO
0 -40 -15 10 35 60 85 TEMPERATURE (C)
0 2.75 3.25 3.75 4.25 4.75 5.25 AVDD OR DVDD (V)
4.09590 4.75 4.85 4.95 5.05 5.15 5.25 VAVDD (V)
6
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4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs
Typical Operating Characteristics (continued)
(VAVDD = 5V, VDVDD = 3.3V, TA = +25C, fSAMPLE = 250ksps, internal reference, unless otherwise noted.)
INTERNAL REFERENCE VOLTAGES vs. TEMPERATURE
MAX11047 toc11
MAX11047-MAX11049/MAX11057-MAX11059
OFFSET ERROR AND OFFSET ERROR MATCHING vs. SUPPLY VOLTAGE
MAX11047 toc12
OFFSET ERROR AND OFFSET ERROR MATCHING vs. TEMPERATURE
fSAMPLE = 250ksps VAVDD = 5.0V VREFIO = 4.096V OFFSET ERROR MATCHING ERRORS (%FS) 0.002
MAX11047 toc13
4.112 VAVDD = 5.0V 4.108 4.104 VREFIO (V) 4.100 4.096 4.092 4.088 4.084 4.080 -40 -15 10 35 60 LOWER TYPICAL LIMIT UPPER TYPICAL LIMIT
0.010
0.010
0.006 ERRORS (%FS)
fSAMPLE = 250ksps TA = +25C VRDC = 4.096V OFFSET ERROR MATCHING
0.006
0.002
-0.002 OFFSET ERROR -0.006
-0.002 OFFSET ERROR -0.006
-0.010 85 4.75 4.85 4.95 5.05 5.15 5.25 TEMPERATURE (C) VAVDD (V)
-0.010 -40 -15 10 35 60 85 TEMPERATURE (C)
GAIN ERROR AND GAIN ERROR MATCHING vs. SUPPLY VOLTAGE
MAX11047 toc14
GAIN ERROR AND GAIN ERROR MATCHING vs. TEMPERATURE
MAX11047 toc15
FFT PLOT FOR MAX1104_
fIN = 10kHz fSAMPLE = 250ksps TA = +25C VAVDD = 5.0V
MAX11047 toc16
0.010
0.006 ERRORS (%FS)
fSAMPLE = 250ksps TA = +25C VRDC = 4.096V GAIN ERROR MATCHING
0.010
0.006 ERRORS (%FS)
fSAMPLE = 250ksps VAVDD = 5.0V VREFIO = 4.096V GAIN ERROR MATCHING
0 -20 MAGNITUDE (dB) -40 -60 -80 -100 -120
0.002
0.002
-0.002 GAIN ERROR
-0.002 GAIN ERROR
-0.006
-0.006
-0.010 4.75 4.85 4.95 5.05 5.15 5.25 VAVDD (V)
-0.010 -40 -15 10 35 60 85 TEMPERATURE (C)
-140 0 25 50 75 100 125 FREQUENCY (kHz)
TWO-TONE IMD PLOT FOR MAX1104_
MAX11047 toc17
SIGNAL-TO-NOISE RATIO (SNR) AND SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) vs. TEMPERATURE FOR MAX1104_
MAX11047 toc18
TOTAL HARMONIC DISTORTION (THD) vs. TEMPERATURE FOR MAX1104_
VAVDD = 5.0V fIN = 10kHz fSAMPLE = 250ksps TA = +25C VRDC = 4.096V VIN = -0.025dB FROM FS
MAX11047 toc19
0 -20 MAGNITUDE (dB) -40 -60 -80 -100 -120 -140 7.6 8.4 9.2 10.0 10.8 11.6 fIN1 = 9834Hz fIN2 = 10384Hz fSAMPLE = 250ksps TA = +25C VAVDD = 5.0V VRDC = 4.096V VIN = -0.01dBFS
93.0
-108.0
SNR AND SINAD (dB)
92.5
SNR
-108.5 THD (dB)
92.0 VAVDD = 5.0V fIN = 10kHz SINAD fSAMPLE = 250ksps TA = +25C VRDC = 4.096V VIN = -0.025dB FROM FS -40 -15 10 35 60 85
-109.0
91.5
-109.5
91.0 12.4 FREQUENCY (kHz) TEMPERATURE (C)
-110.0 -40 -15 10 35 60 85 TEMPERATURE (C)
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4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs MAX11047-MAX11049/MAX11057-MAX11059
Typical Operating Characteristics (continued)
(VAVDD = 5V, VDVDD = 3.3V, TA = +25C, fSAMPLE = 250ksps, internal reference, unless otherwise noted.)
SNR AND SINAD vs. ANALOG SUPPLY VOLTAGE FOR MAX1104_
MAX11047 toc20
THD vs. ANALOG SUPPLY VOLTAGE FOR MAX1104_
MAX11047 toc21
SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) vs. FREQUENCY FOR MAX1104_
MAX11047 toc22
93.0
-108.0
SNR AND SINAD (dB)
92.5
fIN = 10kHz fSAMPLE = 250ksps TA = +25C VRDC = 4.096V VIN = -0.025dB FROM FS
SNR THD (dB)
-108.5
fIN = 10kHz fSAMPLE = 250ksps TA = +25C VRDC = 4.096V VIN = -0.025dB FROM FS
94 93 92 SINAD (dB) 91 90 VAVDD = 5.0V fSAMPLE = 250ksps TA = +25C VRDC = 4.096V VIN = -0.025dB FROM FS 0.1 1.0 10.0
92.0 SINAD 91.5
-109.0
-109.5 89
91.0 4.75 4.85 4.95 5.05 5.15 5.25 VAVDD (V)
-110.0 4.75 4.85 4.95 5.05 5.15 5.25 VAVDD (V)
88
100.0
FREQUENCY (kHz)
THD vs. INPUT FREQUENCY FOR MAX1104_
MAX11047 toc23
CROSSTALK vs. FREQUENCY
MAX11047 toc24
OUTPUT NOISE HISTOGRAM WITH INPUT CONNECTED TO 2.5V FOR MAX1104_
VCHX = 2.500270V VAVDD = 5.0V fSAMPLE = 250ksps TA = +25C
MAX11047 toc25 MAX11047 toc27
-85 -90 -95 THD (dB) -100 -105 -110 -115 -120 0.1
NUMBER OF OCCURENCES
CROSSTALK (dB)
VAVDD = 5.0V fSAMPLE = 250ksps TA = +25C VRDC = 4.096V VIN = -0.025dB FROM FS
-90 fIN = 60Hz fSAMPLE = 250ksps TA = +25C VAVDD = 5.0V VRDC = 4.096V VIN = -0.025dB FROM FS INACTIVE CHANNEL AT GND
24000 20000 16000 12000 8000 4000 0
-100
-110
-120
-130
-140 1.0 10.0 100.0 0.1 1 10 100 FREQUENCY (kHz) FREQUENCY (kHz)
32768 32769 32770 32771 32772 32773 32774 OUTPUT CODE (DECIMAL)
CONVERSION TIME vs. ANALOG SUPPLY VOLTAGE
TA = +25C 2.99 CONVERSION TIME (S) 2.98 2.97 2.96 2.95 2.94 2.93 2.92 4.75 4.85 4.95 5.05 5.15 5.25 VAVDD (V)
MAX11047 toc26
CONVERSION TIME vs. TEMPERATURE
3.00 VAVDD = 5.0V 2.99 CONVERSION TIME (S) 2.98 2.97 2.96 2.95 2.94 2.93 2.92 -40 -15 10 35 60 85 TEMPERATURE (C)
3.00
8
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4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs
Pin Configurations
CH5*/CH4/CH3 CH4*/CH3/CH2 CH3*/CH2/CH1 CH6*/CH5/I.C. CH2*/CH1/CH0 CH1*/CH0/I.C.
MAX11047-MAX11049/MAX11057-MAX11059
AGNDS
CH5*/CH4/CH3
CH4*/CH3/CH2
CH3*/CH2/CH1
CH2*/CH1/CH0
CH6*/CH5/I.C.
CH1*/CH0/I.C.
AGNDS
AGND
AGND
REFIO
AVDD
AVDD
RDC
RDC
AGNDS
AGND
REFIO
AGND
AVDD
RDC
AVDD
TOP VIEW
AGNDS
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 AGNDS 31 CH0*/I.C. 30 AGND 29 AVDD 28 AGNDS 27 RDC 26 RDC_SENSE
42 41 40 39 38 37 36 35 34 33 32 31 30 29 RDC 43 AGNDS 44 I.C./CH7* 45 AGND 46 AVDD 47 AGNDS 48 RDC 49 DGND 50 DVDD 51 WR 52 CS 53 RD 54 DB15 55 DB14 56 1 DB13 2 DB12 3 DB11 4 DB10 5 DB9 6 DB8 7 DGND 8 DVDD 9 DB7 10 11 12 13 14 DB6 DB5 DB4 DB3/CR3 DB2/CR2 *EP 28 RDC 27 AGNDS 26 CH0*/I.C. 25 AGND 24 AVDD 23 AGNDS
AGNDS 49 I.C./CH7* 50 AGND 51 AVDD 52 AGNDS 53 RDC 54 RDC_SENSE 55 AGND 56 AVDD 57 AGNDS 58 DGND 59 DVDD 60 WR 61 CS 62 RD 63 DB15 64 *EP
MAX11047 MAX11048 MAX11049
22 RDC 21 DGND 20 DVDD 19 SHDN 18 CONVST 17 EOC
MAX11047 MAX11048 MAX11049
RDC
25 AGND 24 AVDD 23 AGNDS 22 DGND 21 DVDD 20 SHDN 19 CONVST
+
16 DB0/CR0 15 DB1/CR1
+
18 EOC 17 DB0/CR0
DB3/CR3
DB2/CR2
*MAX11049
TQFP 10mm x 10mm
CH5*/CH4/CH3 CH4*/CH3/CH2 CH3*/CH2/CH1 CH2*/CH1/CH0 CH6*/CH5/I.C. CH1*/CH0/I.C.
AGNDS
AGNDS
AGND
AGND
REFIO
AVDD
AVDD
RDC
RDC
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 AGNDS 31 CH0*/I.C. 30 AGND 29 AVDD 28 AGNDS 27 RDC 26 RDC_SENSE
AGNDS 49 I.C./CH7* 50 AGND 51 AVDD 52 AGNDS 53 RDC 54 RDC_SENSE 55 AGND 56 AVDD 57 AGNDS 58 DGND 59 DVDD 60 WR 61 CS 62 RD 63 DB13 64 *EP
MAX11057 MAX11058 MAX11059
RDC
25 AGND 24 AVDD 23 AGNDS 22 DGND 21 DVDD 20 SHDN 19 CONVST
+
18 EOC 17 CR0
1 DB12
2 DB11
3 DB10
4 DB9
5 DB8
6 DB7
7 DB6
8 DGND
9 DVDD
10 11 12 13 14 15 16 DB5 DB4 DB3 DB2 DB1/CR3 DB0/CR2 CR1
MAX11057 MAX11058
*MAX11059
TQFP 10mm x 10mm
_______________________________________________________________________________________
DB1/CR1
TQFN 8mm x 8mm
DB9
DB8
DB7
DB6
DB5
DB14
DB13
DB12
DB11
DB10
DGND
DVDD
DB4
MAX11047 MAX11048
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
9
4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs MAX11047-MAX11049/MAX11057-MAX11059
Pin Description
PIN MAX11047 (TQFN-EP) 1 2 3 4 5 6 7, 21, 50 8, 20, 51 9 10 11 12 13 14 15 16 17 MAX11048 (TQFN-EP) 1 2 3 4 5 6 7, 21, 50 8, 20, 51 9 10 11 12 13 14 15 16 17 MAX11049 (TQFN-EP) 1 2 3 4 5 6 7, 21, 50 8, 20, 51 9 10 11 12 13 14 15 16 17 NAME DB13 DB12 DB11 DB10 DB9 DB8 DGND DVDD DB7 DB6 DB5 DB4 DB3/CR3 DB2/CR2 DB1/CR1 DB0/CR0 EOC FUNCTION 16-Bit Parallel Data Bus Digital Output Bit 13 16-Bit Parallel Data Bus Digital Output Bit 12 16-Bit Parallel Data Bus Digital Output Bit 11 16-Bit Parallel Data Bus Digital Output Bit 10 16-Bit Parallel Data Bus Digital Output Bit 9 16-Bit Parallel Data Bus Digital Output Bit 8 Digital Ground Digital Supply. Bypass to DGND with a 0.1F capacitor at each DVDD input. 16-Bit Parallel Data Bus Digital Output Bit 7 16-Bit Parallel Data Bus Digital Output Bit 6 16-Bit Parallel Data Bus Digital Output Bit 5 16-Bit Parallel Data Bus Digital Output Bit 4 16-Bit Parallel Data Bus Digital Output Bit 3/Configuration Register Input Bit 3 16-Bit Parallel Data Bus Digital Output Bit 2/Configuration Register Input Bit 2 16-Bit Parallel Data Bus Digital Output Bit 1/Configuration Register Input Bit 1 16-Bit Parallel Data Bus Digital Output Bit 0/Configuration Register Input Bit 0 Active-Low End of Conversion Output. EOC goes low when conversion is completed. EOC goes high when a conversion is initiated. Convert Start Input. Rising edge of CONVST ends sample and starts a conversion on the captured sample. The ADC is in acquisition mode when CONVST is low and CONVST mode = 0. Shutdown Input. If SHDN is held high, the entire device enters and stays in a low-current state. Contents of the Configuration register are not lost when in the shutdown state. Reference Buffer Decoupling. Connect all RDC outputs together. Bypass to AGND with at least an 80F total capacitance. See the Layout, Grounding, and Bypassing section. Signal Ground. Connect all AGND and AGNDS inputs together on PWB. Analog Supply Input. Bypass AVDD to AGND with a 0.1F capacitor at each AVDD input. Analog Ground. Connect all AGND inputs together. Internally Connected. Connect to AGND Channel 0 Analog Input Channel 1 Analog Input External Reference Input/Internal Reference Output. Place a 0.1F capacitor from REFIO to AGND.
18
18
18
CONVST
19
19
19
SHDN
22, 28, 35, 43, 49 23, 27, 33, 38, 44, 48 24, 30, 41, 47 25, 31, 40, 46 26, 29, 42, 45 32 34 36
22, 28, 35, 43, 49 23, 27, 33, 38, 44, 48 24, 30, 41, 47 25, 31, 40, 46 26, 45 29 32 36
22, 28, 35, 43, 49 23, 27, 33, 38, 44, 48 24, 30, 41, 47 25, 31, 40, 46 -- 26 29 36
RDC
AGNDS AVDD AGND I.C. CH0 CH1 REFIO
10
______________________________________________________________________________________
4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs
Pin Description (continued)
PIN MAX11047 (TQFN-EP) 37 39 -- -- -- -- 52 53 54 55 56 -- MAX11048 (TQFN-EP) 34 37 39 42 -- -- 52 53 54 55 56 -- MAX11049 (TQFN-EP) 32 34 37 39 42 45 52 53 54 55 56 -- NAME CH2 CH3 CH4 CH5 CH6 CH7 WR CS RD DB15 DB14 EP Channel 2 Analog Input Channel 3 Analog Input Channel 4 Analog Input Channel 5 Analog Input Channel 6 Analog Input Channel 7 Analog Input Active-Low Write Input. Drive WR low to write to the ADC. Configuration registers are loaded on the rising edge of WR. Active Low-Chip Select Input. Drive CS low when reading from or writing to the ADC. Active-Low Read Input. Drive RD low to read from the ADC. Each rising edge of RD advances the channel output on the data bus. 16-Bit Parallel Data Bus Digital Output Bit 15 16-Bit Parallel Data Bus Digital Output Bit 14 Exposed Pad. Internally connected to AGND. Connect to a large ground plane to maximize thermal performance. Not intended as an electrical connection point. FUNCTION
MAX11047-MAX11049/MAX11057-MAX11059
PIN MAX11047 (TQFP-EP) 1 2 3 4 5 6 7 8, 22, 59 9, 21, 60 10 11 12 13 14 15 16 17 MAX11048 (TQFP-EP) 1 2 3 4 5 6 7 8, 22, 59 9, 21, 60 10 11 12 13 14 15 16 17 MAX11049 (TQFP-EP) 1 2 3 4 5 6 7 8, 22, 59 9, 21, 60 10 11 12 13 14 15 16 17 NAME DB14 DB13 DB12 DB11 DB10 DB9 DB8 DGND DVDD DB7 DB6 DB5 DB4 DB3/CR3 DB2/CR2 DB1/CR1 DB0/CR0 FUNCTION 16-Bit Parallel Data Bus Digital Output Bit 14 16-Bit Parallel Data Bus Digital Output Bit 13 16-Bit Parallel Data Bus Digital Output Bit 12 16-Bit Parallel Data Bus Digital Output Bit 11 16-Bit Parallel Data Bus Digital Output Bit 10 16-Bit Parallel Data Bus Digital Output Bit 9 16-Bit Parallel Data Bus Digital Output Bit 8 Digital Ground Digital Supply. Bypass to DGND with a 0.F capacitor at each DVDD input. 16-Bit Parallel Data Bus Digital Output Bit 7 16-Bit Parallel Data Bus Digital Output Bit 6 16-Bit Parallel Data Bus Digital Output Bit 5 16-Bit Parallel Data Bus Digital Output Bit 4 16-Bit Parallel Data Bus Digital Output Bit 3/Configuration Register Input Bit 3 16-Bit Parallel Data Bus Digital Output Bit 2/Configuration Register Input Bit 2 16-Bit Parallel Data Bus Digital Output Bit 1/Configuration Register Input Bit 1 16-Bit Parallel Data Bus Digital Output Bit 0/Configuration Register Input Bit 0
______________________________________________________________________________________
11
4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs MAX11047-MAX11049/MAX11057-MAX11059
Pin Description (continued)
PIN MAX11047 (TQFP-EP) 18 MAX11048 (TQFP-EP) 18 MAX11049 (TQFP-EP) 18 NAME FUNCTION
EOC
Active-Low, End-of-Conversion Output. EOC goes low when a conversion is completed. EOC goes high when a conversion is initiated. Convert Start Input. The rising edge of CONVST ends sample and starts a conversion on the captured sample. The ADC is in acquisition mode when CONVST is low and CONVST mode = 0. Shutdown Input. If SHDN is held high, the entire device enters and stays in a low-current state. Contents of the Configuration register are not lost when in the shutdown state. Signal Ground. Connect all AGND and AGNDS inputs together. Analog Supply Input. Bypass AVDD to AGND with a 0.1F capacitor at each AVDD input. Analog Ground. Connect all AGND inputs together.
19
19
19
CONVST
20 23, 28, 32, 38, 43, 49, 53, 58 24, 29, 35, 46, 52, 57 25, 30, 36, 45, 51, 56 26, 55 27, 33, 40, 48, 54 31, 34, 47, 50 37 39 41 42 44 -- -- -- -- 61 62 63 64 --
20 23, 28, 32, 38, 43, 49, 53, 58 24, 29, 35, 46, 52, 57 25, 30, 36, 45, 51, 56 26, 55 27, 33, 40, 48, 54 31, 50 34 37 41 39 42 44 47 -- -- 61 62 63 64 --
20 23, 28, 32, 38, 43, 49, 53, 58 24, 29, 35, 46, 52, 57 25, 30, 36, 45, 51, 56 26, 55 27, 33, 40, 48, 54 -- 31 34 41 37 39 42 44 47 50 61 62 63 64 --
SHDN
AGNDS
AVDD AGND
RDC_SENSE Reference Buffer Sense Feedback. Connect to RDC plane. RDC Reference Buffer Decoupling. Connect all RDC outputs together. Bypass to AGND with at least an 80F total capacitance. See the Layout, Grounding, and Bypassing section. Internally Connected. Connect to AGND. Channel 0 Analog Input Channel 1 Analog Input External Reference Input/Internal Reference Output. Place a 0.1F capacitor from REFIO to AGND. Channel 2 Analog Input Channel 3 Analog Input Channel 4 Analog Input Channel 5 Analog Input Channel 6 Analog Input Channel 7 Analog Input Active-Low Write Input. Drive WR low to write to the ADC. Configuration registers are loaded on the rising edge of WR. Active-Low Chip-Select Input. Drive CS low when reading from or writing to the ADC. Active-Low Read Input. Drive RD low to read from the ADC. Each rising edge of RD advances the channel output on the data bus. 16-Bit Parallel Data Bus Digital Out Bit 15 Exposed Pad. Internally connected to AGND. Connect to a large ground plane to maximize thermal performance. Not intended as an electrical connection point.
I.C. CH0 CH1 REFIO CH2 CH3 CH4 CH5 CH6 CH7 WR CS RD DB15 EP
12
______________________________________________________________________________________
4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs
Pin Description (continued)
PIN MAX11057 (TQFP-EP) 1 2 3 4 5 6 7 8, 22, 59 9, 21, 60 10 11 12 13 14 15 16 17 18 MAX11058 (TQFP-EP) 1 2 3 4 5 6 7 8, 22, 59 9, 21, 60 10 11 12 13 14 15 16 17 18 MAX11059 (TQFP-EP) 1 2 3 4 5 6 7 8, 22, 59 9, 21, 60 10 11 12 13 14 15 16 17 18 NAME DB12 DB11 DB10 DB9 DB8 DB7 DB6 DGND DVDD DB5 DB4 DB3 DB2 DB1/CR3 DB0/CR2 CR1 CR0 EOC FUNCTION 14-Bit Parallel Data Bus Digital Output Bit 12 14-Bit Parallel Data Bus Digital Output Bit 11 14-Bit Parallel Data Bus Digital Output Bit 10 14-Bit Parallel Data Bus Digital Output Bit 9 14-Bit Parallel Data Bus Digital Output Bit 8 14-Bit Parallel Data Bus Digital Output Bit 7 14-Bit Parallel Data Bus Digital Output Bit 6 Digital Ground Digital Supply. Bypass to DGND with a 0.1F capacitor at each DVDD input. 14-Bit Parallel Data Bus Digital Output Bit 5 14-Bit Parallel Data Bus Digital Output Bit 4 14-Bit Parallel Data Bus Digital Output Bit 3 14-Bit Parallel Data Bus Digital Output Bit 2 14-Bit Parallel Data Bus Digital Output Bit 1/Configuration Register Input Bit 3 14-Bit Parallel Data Bus Digital Output Bit 0/Configuration Register Input Bit 2 Configuration Register Input Bit 1 Configuration Register Input Bit 0 Active-Low, End-of-Conversion Output. EOC goes low when a conversion is completed. EOC goes high when a conversion is initiated. Convert Start Input. The rising edge of CONVST ends sample and starts a conversion on the captured sample. The ADC is in acquisition mode when CONVST is low and CONVST mode = 0. Shutdown Input. If SHDN is held high, the entire device enters and stays in a low-current state. Contents of the Configuration register are not lost when in the shutdown state. Signal Ground. Connect all AGND and AGNDS inputs together. Analog Supply Input. Bypass AVDD to AGND with a 0.1F capacitor at each AVDD input. Analog Ground. Connect all AGND inputs together.
MAX11047-MAX11049/MAX11057-MAX11059
19
19
19
CONVST
20 23, 28, 32, 38, 43, 49, 53, 58 24, 29, 35, 46, 52, 57 25, 30, 36, 45, 51, 56 26, 55 27, 33, 40,48, 54 31, 34, 47, 50 37 39
20 23, 28, 32, 38, 43, 49, 53, 58 24, 29, 35, 46, 52, 57 25, 30, 36, 45, 51, 56 26, 55 27, 33, 40,48, 54 31, 50 34 37
20 23, 28, 32, 38, 43, 49, 53, 58 24, 29, 35, 46, 52, 57 25, 30, 36, 45, 51, 56 26, 55 27, 33, 40,48, 54 -- 31 34
SHDN
AGNDS
AVDD AGND
RDC_SENSE Reference Buffer Sense Feedback. Connect to RDC plane. RDC Reference Buffer Decoupling. Connect all RDC outputs together. Bypass to AGND with at least an 80F total capacitance. See the Layout, Grounding, and Bypassing section. Internally Connected. Connect to AGND. Channel 0 Analog Input Channel 1 Analog Input
I.C. CH0 CH1
______________________________________________________________________________________
13
4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs MAX11047-MAX11049/MAX11057-MAX11059
Pin Description (continued)
PIN MAX11057 (TQFP-EP) 41 42 44 -- -- -- -- 61 62 63 64 -- MAX11058 (TQFP-EP) 41 39 42 44 47 -- -- 61 62 63 64 -- MAX11059 (TQFP-EP) 41 37 39 42 44 47 50 61 62 63 64 -- NAME FUNCTION External Reference Input/Internal Reference Output. Place a 0.1F capacitor from REFIO to AGND. Channel 2 Analog Input Channel 3 Analog Input Channel 4 Analog Input Channel 5 Analog Input Channel 6 Analog Input Channel 7 Analog Input Active-Low Write Input. Drive WR low to write to the ADC. Configuration registers are loaded on the rising edge of WR. Active-Low Chip-Select Input. Drive CS low when reading from or writing to the ADC. Active-Low Read Input. Drive RD low to read from the ADC. Each rising edge of RD advances the channel output on the data bus. 14-Bit Parallel Data Bus Digital Out Bit 13 Exposed Pad. Internally connected to AGND. Connect to a large ground plane to maximize thermal performance. Not intended as an electrical connection point.
REFIO CH2 CH3 CH4 CH5 CH6 CH7 WR CS RD DB13 EP
Detailed Description
The MAX11047/MAX11048/MAX11049 and MAX11057/ MAX11058/MAX11059 are fast, low-power ADCs that combine 4, 6, or 8 independent ADC channels in a single IC. Each channel includes simultaneously sampling independent T/H circuitry that preserves relative phase information between inputs making the devices ideal for motor control and power monitoring. The devices are available with a 0 to 5V input range that features 20mA overrange, fault-tolerant inputs. The devices operate with a single 4.75V to 5.25V supply. A separate 2.7V to 5.25V supply for digital circuitry makes the devices compatible with low-voltage processors. The devices perform conversions for all channels in parallel by activating independent ADCs. Results are available through a high-speed, 20MHz, parallel data bus after a conversion time of 3s following the end of a sample. The
data bus is bidirectional and allows for easy programming of the configuration register. The devices feature a reference buffer, which is driven by an internal bandgap reference circuit (VREFIO = 4.096V). Drive REFIO with an external reference or bypass with a 0.1F capacitor to ground when using the internal reference.
Analog Inputs
Track and Hold (T/H) To preserve phase information across all channels, each input includes a dedicated T/H circuitry. The input tracking circuitry provides a 4MHz small-signal bandwidth, enabling the device to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the ADC's sampling rate by using undersampling techniques. Use anti-alias filtering to avoid high-frequency signals being aliased into the frequency band of interest.
14
______________________________________________________________________________________
4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs
Input Range and Protection
The full-scale analog input voltage is a product of the reference voltage. For the devices, the input is unipolar in the range of: 0 to + VREFIO x 5.0 4.096 of 0V to +V AVDD , the clamps begin to turn on. Consequently, to obtain the highest accuracy, ensure that the input voltage does not exceed the range of 0V to +VAVDD. To make use of the input clamps, connect a resistor (RS) between the analog input and the voltage source to limit the voltage at the analog input so that the fault current into the devices does not exceed 20mA. Note that the voltage at the analog input pin limits to approximately 7V during a fault condition so the following equation can be used to calculate the value of RS: RS = VFAULT _ MAX - 7V 20mA
MAX11047-MAX11049/MAX11057-MAX11059
In external reference mode, drive VREFIO with a 3.0V to 4.25V source, resulting in a full-scale input range of 3.662V to 5.188V, respectively. All analog inputs are fault-protected up to 20mA. The devices include an input clamping circuit that activates when the input voltage at the analog input is above (VAVDD + 300mV) or below -300mV. The clamp circuit remains high impedance while the input signal is within the range of 0V to +VAVDD and draws little to no current. However, when the input signal exceeds the range
where VFAULT_MAX is the maximum voltage that the source produces during a fault condition.
INPUT SIGNAL RS
PIN VOLTAGE AVDD
DVDD DB15**
8 x 16-/14-BIT REGISTERS
SOURCE
BIDIRECTIONAL DRIVERS
CH0
CLAMP
S/H
16-/14-BIT ADC
DB4 DB3/CR3 DB0/CR0
CH7
CLAMP
S/H
16-/14-BIT ADC
AGNDS
CONFIGURATION REGISTERS INTERFACE AND CONTROL
WRb RDb CSb CONVST SHDN EOCb DGND RDC RDC_SENSE*
AGND MAX11047/MAX11048/MAX11049/ MAX11057/MAX11058/MAX11059 INT REF 10k BANDGAP REFERENCE REFIO EXT REF *CONNECTED INTERNALLY ON THE TQFN PARTS **MAX11047/MAX11048/MAX11049
REF BUF
MAX11049/MAX11059
Figure 1. Required Setup for Clamp Circuit
______________________________________________________________________________________
15
4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs MAX11047-MAX11049/MAX11057-MAX11059
25 20 15 10 ICLAMP (mA) 5 0 -5 -10 -15 -20 -25 -30 -20 -10 0 10 20 30 40 SIGNAL VOLTAGE AT SOURCE AND CH_ INPUT (V) AT SOURCE AT CH_ INPUT ICLAMP (mA) RS = 1170I VAVDD = 5.0V 25 20 15 10 5 0 -5 -10 -15 -20 -25 -4 -2 0 2 4 6 8 SIGNAL VOLTAGE AT SOURCE AND CH_ INPUT (V) AT SOURCE AT CH_ INPUT RS = 1170I VAVDD = 5.0V
Figure 2. Input Clamp Characteristics
Figure 3. Input Clamp Characteristics (Zoom In)
Figures 2 and 3 illustrate the clamp circuit voltage-current characteristics for a source impedance R S = 1280. While the input voltage is within the -300mV to +(VAVDD + 300mV) range, no current flows in the input clamps. Once the input voltage goes beyond this voltage range, the clamps turn on and limit the voltage at the input pin.
CR1 (Reserved)
CR1 must be set to 0.
Applications Information
Digital Interface
The bidirectional, parallel, digital interface, CR0-CR3, sets the 4-bit configuration register. This interface configures the following control signals: chip select (CS), read (RD), write (WR), end of conversion (EOC), and convert start (CONVST). Figures 6 and 7 and the Timing Characteristics in the Electrical Characteristics table show the operation of the interface. DB0-DB15/13, output the 16-/14-bit conversion result. All bits are high impedance when RD = 1 or CS = 1.
CR0 (CONVST Mode) CR0 selects the acquisition mode. The POR default = 0. 0 = CONVST controls the acquisition and conversion. Drive CONVST low to start acquisition. The rising edge of CONVST begins the conversion. 1 = acquisition mode starts as soon as previous conversion is complete. The rising edge of CONVST begins the conversion. Programming the Configuration Register To program the configuration register, bring the CS and WR low and apply the required configuration data on CR3-CR0 of the bus and then raise WR once to save changes. CAUTION: The host driving CR3-CR0 must relinquish the bus when the conversion results of the ADC are being read.
CR3 (Int/Ext Reference) CR3 selects the internal or external reference. The POR default = 0. 0 = internal reference, REFIO internally driven through a 10k resistor, bypass with 0.1F capacitor to AGND. 1 = external reference, drive REFIO with a high quality reference. CR2 (Output Data Format) CR2 selects the output data format. The POR default = 0. 0 = offset binary. 1 = two's complement.
Starting a Conversion
CONVST initiates conversions. The devices provide two acquisition modes set through the configuration register. Allow a quiet time (tQ) of 500ns prior to the start of conversion to avoid any noise interference during readout or write operations from corrupting a sample.
Table 1. Configuration Register
CR3 Int/Ext Reference CR2 Output Data Format CR1 Must be set to 0 CR0 CONVST Mode
16
______________________________________________________________________________________
4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs
In default mode (CR0 = 0), drive CONVST low to place the devices into acquisition mode. All the input switches are closed and the internal T/H circuits track the respective input voltage. Keep the CONVST signal low for at least 1s (tACQ) to enable proper settling of the sampled voltages. On the rising edge of CONVST, the switches are opened and the devices begin the conversion on all the samples in parallel. EOC remains high until the conversion is completed. In the second mode (CR0 = 1), the devices enter acquisition mode as soon as the previous conversion is completed. CONVST rising edge initiates the next sample and conversion sequence. Drive CONVST low for at least 20ns to be valid. Provide adequate time for acquisition and the requisite quiet time in both modes to achieve accurate sampling and maximum performance of the devices. together. The reference buffer is externally compensated and requires at least 10F on the RDC node for stability. For best performance, provide a total of at least 80F on the RDC outputs.
MAX11047-MAX11049/MAX11057-MAX11059
Transfer Functions
Figures 8 and 9 show the transfer functions for all the formats and devices. Code transitions occur halfway between successive-integer LSB values.
Layout, Grounding, and Bypassing
For best performance, use PCBs with ground planes. Ensure that digital and analog signal lines are separated from each other. Do not run analog and digital lines parallel to one another (especially clock lines), and avoid running digital lines underneath the ADC package. A single solid GND plane configuration with digital signals routed from one direction and analog signals from the other provides the best performance. Connect DGND, AGND, and AGNDS pins on the devices to this ground plane. Keep the ground return to the power supply for this ground low impedance and as short as possible for noise-free operation. To achieve the highest performance, connect all the RDC pins 22, 28, 35, 43, and 49 for the TQFN package or pins 27, 33, 40, 48, and 54 for the TQFP package to a local RDC plane on the PCB. In addition, on the TQFP package, the RDC_SENSE pins 26 and 55 should be directly connected to this RDC plane as well. Bypass the RDC outputs with a total of at least 80F of capacitance. For example, if two capacitors are used, place two 47F, 10V X5R capacitors in 1210 case size as close as possible to pins 22 and 49 (TQFN), or pins 27 and 54 (TQFP). Alternatively, if four capacitors are used, place four 22F, 10V X5R capacitors in 1210 case size as close as possible to pins 22, 28, 43, and 49 (TQFN), or pins 27, 33, 48, and 54 (TQFP). Ensure that each capacitor is connected directly into the GND plane with an independent via. In cases where Y5U or Z5U ceramics are used, select higher voltage rating capacitors to compensate for the high-voltage coefficient of these ceramic capacitors, thus ensuring that at least 80F of capacitance is on the RDC plane when the plane is driven to 4.096V by the internal reference buffer. For example, at 4.096V, a 22F X5R ceramic capacitor with a 10V rating diminishes to only 20F, whereas the same capacitor in Y5U ceramic at 4.096V decreases to about 13F. However, a 22F Y5U ceramic capacitor with a 25V rating capacitor is approximately 20F at 4.096V.
Reading Conversion Results
The CS and RD are active-low, digital inputs that control the readout through the 16-/14-bit, parallel, 20MHz data bus (D0-D15/13). After EOC transitions low, read the conversion data by driving CS and RD low. Each low period of RD presents the next channel's result. When CS or RD are high, the data bus is high impedance. CS may be driven high between individual channel readouts or left low during the entire 8-channel readout.
Reference
Internal Reference The devices feature a precision, low-drift, internal bandgap reference. Bypass REFIO with a 0.1F capacitor to AGND to reduce noise. The REFIO output voltage may be used as a reference for other circuits. The output impedance of REFIO is 10k. Drive only high-impedance circuits or buffer externally when using REFIO to drive external circuitry. External Reference Set the configuration register to disable the internal reference and drive REFIO with a high-quality external reference. To avoid signal degradation, ensure that the integrated reference noise applied to REFIO is less than 10V in the bandwidth of up to 50kHz. Reference Buffer The devices have a built- in reference buffer to provide a low-impedance reference source to the SAR converters. This buffer is used in both internal and external reference modes. The internal reference buffer output feeds five RDC outputs. Connect all RDC outputs
______________________________________________________________________________________
17
4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs MAX11047-MAX11049/MAX11057-MAX11059
Bypass AVDD and DVDD to the ground plane with 0.1F ceramic chip capacitors on each pin as close as possible to the device to minimize parasitic inductance. Add at least one bulk 10F decoupling capacitor to AVDD and DVDD per PCB. Interconnect all of the AVDD inputs and DVDD inputs using two solid power planes. For best performance, bring the AVDD power plane in on the analog interface side of the devices and the DVDD power plane from the digital interface side of the devices. For sampling periods near minimum (1s) use a 1nF C0G ceramic chip capacitor between each of the channel inputs to the ground plane as close as possible to the devices. This capacitor reduces the inductance seen by the sampling circuitry and reduces the voltage transient seen by the input source circuit.
CS (USER SUPPLIED) t5 t3 WR (USER SUPPLIED) t7 t6 CONFIGURATION REGISTER t4
CR0-CR3 (USER SUPPLIED)
Figure 4. Programming Configuration-Register Timing Requirements
CS (USER SUPPLIED) t8 RD (USER SUPPLIED) t12 Sn t13 t9 t10 t11
DB0-DB15
Sn + 1
Figure 5. Readout Timing Requirements
18
______________________________________________________________________________________
4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs MAX11047-MAX11049/MAX11057-MAX11059
SAMPLE
tCON CONVST
tACQ
t1 EOC
tO
tQ
CS
RD
DB0-DB15 S0 S1 S6 S7
Figure 6. Conversion Timing Diagram (CR0 = 0)
SAMPLE
tCON CONVST
tACQ
t2 EOC
tO
tQ
CS
RD
DB0-DB15 S0 S1 S6 S7
Figure 7. Conversion Timing Diagram (CR0 = 1)
______________________________________________________________________________________ 19
4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs MAX11047-MAX11049/MAX11057-MAX11059
7FFF 7FFE OUTPUT CODE (hex) OUTPUT CODE (hex) VLSB = FS 65536 FULL-SCALE TRANSITION 1FFF 1FFE VLSB = FS 16384 FULL-SCALE TRANSITION
0001 0000 FFFF FFFE
0001 0000 3FFF 3FFE
8001 8000 0 FS/2 INPUT VOLTAGE (LSB) OUTPUT CODE = VIN x 65536 - 32768, 5 VREFIO x 4.096 FS = 5 x VREF 4.096 +FS
2001 2000 0 FS/2 INPUT VOLTAGE (LSB) OUTPUT CODE = VIN x 16384 - 8192, 5 VREFIO x 4.096 FS = 5 x VREF 4.096 +FS
Figure 8a. Two's Complement Transfer Function for 16-Bit Devices
Figure 8b. Two's Complement Transfer Function for 14-Bit Devices
FFFF FFFE OUTPUT CODE (hex)
VLSB =
FS 65536
FULL-SCALE TRANSITION
3FFF 3FFE OUTPUT CODE (hex)
VLSB =
FS 16384
FULL-SCALE TRANSITION
8001 8000 7FFF 7FFE
2001 2000 1FFF 1FFE
0001 0000 0 FS/2 INPUT VOLTAGE (LSB) OUTPUT CODE = 5 x VREF VIN x 65536 , FS = 4.096 5 4.096 +FS
0001 0000 0 FS/2 INPUT VOLTAGE (LSB) OUTPUT CODE = 5 x VREF VIN x 16384 , FS = 4.096 5 4.096 +FS
VREFIO x
VREFIO x
Figure 9a. Offset-Binary Transfer Function for 16-Bit Devices
20
Figure 9b. Offset-Binary Transfer Function for 14-Bit Devices
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4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs
Typical Application Circuits
Power-Grid Protection Figure 10 shows a typical power-grid protection application. DSP Motor Control Figure 11 shows a typical DSP motor control application.
MAX11047-MAX11049/MAX11057-MAX11059
PHASE 1
VOLTAGE TRANSFORMER OPT
2.5V
ADC OPT CURRENT TRANSFORMER VN ADC 2.5V ADC
NEUTRAL
IN
ADC
LOAD 1
MAX11049 MAX11059
LOAD 2 LOAD 3 I3 ADC
V3 I2 PHASE 2 V2
ADC
ADC
ADC PHASE 3
Figure 10. Power-Grid Protection
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21
4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs MAX11047-MAX11049/MAX11057-MAX11059
DSP-BASED DIGITAL PROCESSING ENGINE
MAX1104x MAX1105x
16-/14-BIT ADCs
IGBT CURRENT DRIVERS 16-/14-BIT ADCs 16-/14-BIT ADCs 16-/14-BIT ADCs 16-/14-BIT ADCs
IPHASE1 IPHASE3 IPHASE2
3-PHASE ELECTRIC MOTOR
POSITION ENCODER
Figure 11. DSP Motor Control
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4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs
Definitions
Integral Nonlinearity (INL) INL is the deviation of the values on an actual transfer function from a straight line. For these devices, this straight line is a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. Differential Nonlinearity (DNL) DNL is the difference between an actual step width and the ideal value of 1 LSB. For these devices, the DNL of each digital output code is measured and the worst-case value is reported in the Electrical Characteristics table. A DNL error specification of greater than -1 LSB guarantees no missing codes and a monotonic transfer function for an SAR ADC. For example, -0.9 LSB guarantees no missing code while -1.1 LSB results in missing code. Offset Error For the MAX11047/MAX11048/MAX11049, the offset error is defined at code transition 0x0000 to 0x0001 in offset binary encoding and 0x8000 to 0x8001 for two's complement encoding. For the MAX11057/MAX11058/ MAX11059, the offset error is defined at code transition 0x0000 to 0x0001 in offset binary encoding and 0x2000 to 0x2001 for two's complement encoding. The offset code transitions should occur with an analog input voltage of exactly 0.5 x (5/4.096) x VREF/65,536 above GND for 16-bit devices or 0.5 x (5/4.096) x VREF/16384 above GND for 14-bit devices. The offset error is defined as the deviation between the actual analog input voltage required to produce the offset code transition and the ideal analog input of 0.5 x (5/4.096) x VREF/65,536 above GND for 16-bit devices or 0.5 x (5/4.096) x VREF/16384 above GND for 14-bit devices, expressed in LSBs. Gain Error Gain error is defined as the difference between the change in analog input voltage required to produce a top code transition minus a bottom code transition, subtracted from the ideal change in analog input voltage on (5/4.096) x VREF x (65,534/65,536) for 16-bit or (5/4.096) x VREF x (16382/16384) for 14-bit devices. For the devices, top code transition is 0x7FFE to 0x7FFF in two's complement mode and 0xFFFE to 0xFFFF in offset binary mode. The bottom code transition is 0x8000 and 0x8001 in two's complement mode and 0x0000 and 0x0001 in offset binary mode. For the MAX11057/MAX11058/MAX11059, top code transition is 0x1FFE to 0x1FFF in two's complement mode and 0x3FFE to 0x3FFF in offset binary mode. The bottom code transition is 0x2000 and 0x2001 in two's
complement mode and 0x0000 to 0x0001 in offset binary mode. For the devices, the analog input voltage to produce these code transitions is measured and the gain error is computed by subtracting (5/4.096) x VREF x (65,534/65,536) or (5/4.096) x VREF x (16382/16384), respectively, from this measurement.
MAX11047-MAX11049/MAX11057-MAX11059
Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization noise error only and results directly from the ADC's resolution (N bits): SNR = (6.02 x N + 1.76)dB
where N = 16/14 bits. In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components not including the fundamental, the first five harmonics, and the DC offset.
Signal-to-Noise Plus Distortion (SINAD) SINAD is the ratio of the fundamental input frequency's RMS amplitude to the RMS equivalent of all the other ADC output signals:
Signal RMS SINAD(dB) = 10 x log (Noise + Distortion) RMS
Effective Number of Bits (ENOB) The ENOB indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC's error consists of quantization noise only. With an input range equal to the full-scale range of the ADC, calculate the ENOB as follows:
ENOB = SINAD - 1. 76 6. 02
Total Harmonic Distortion (THD) THD is the ratio of the RMS of the first five harmonics of the input signal to the fundamental itself. This is expressed as:
V2 2 + V3 2 + V4 2 + V 5 2 THD = 20 x log V1
where V1 is the fundamental amplitude and V2 through V5 are the 2nd- through 5th-order harmonics.
23
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4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs MAX11047-MAX11049/MAX11057-MAX11059
Spurious-Free Dynamic Range (SFDR) SFDR is the ratio of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest frequency component. Aperture Delay Aperture delay (tAD) is the time delay from the sampling clock edge to the instant when an actual sample is taken. Aperture Jitter Aperture Jitter (tAJ) is the sample-to-sample variation in aperture delay. Channel-to-Channel Isolation Channel-to-channel isolation indicates how well each analog input is isolated from the other channels. Channelto-channel isolation is measured by applying DC to channels 1 to 7, while a -0.4dBFS sine wave at 60Hz is applied to channel 0. A 10ksps FFT is taken for channel 0 and channel 1. Channel-to-channel isolation is expressed in dB as the power ratio of the two 60Hz magnitudes. Small-Signal Bandwidth A small -20dBFS analog input signal is applied to an ADC in a manner that ensures that the signal's slew rate does not limit the ADC's performance. The input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased 3dB. Full-Power Bandwidth A large -0.5dBFS analog input signal is applied to an ADC, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by 3dB. This point is defined as fullpower input bandwidth frequency.
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 56 TQFN-EP 64 TQFP-EP PACKAGE CODE T5688+2 C64E+6 OUTLINE NO. 21-0135 21-0084 LAND PATTERN NO. 90-0046 90-0328
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4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs
Revision History
REVISION NUMBER 0 1 2 REVISION DATE 12/09 6/10 1/11 Initial release Released MAX11047, MAX11048, and MAX11049 in TQFP packages Released MAX11057, MAX11058, and MAX11059. Updated Electrical Characteristics and Typical Operating Characteristics. DESCRIPTION PAGES CHANGED -- 1-20 1-8
MAX11047-MAX11049/MAX11057-MAX11059
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 25
(c) 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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